1. Field of the Invention
This invention is concerned with apparatus for and a method of effecting address translation in a multi-microprocessor implemented data processing system that emulates a mainframe system. More particularly, this invention is directed to optimizing dynamic address translation in such a system through the replacement of the translation look-aside buffer with a random access memory array.
2. Description of the Prior Art
The emulation of "mainframe" data processing systems through the use of microprocessors has become a reality. A typical mainframe data processing system would be any one of the System/370 (S/370) models available from International Business Machines Corporation. The Personal Computer XT/370, a "desktop" System/370, also available from International Business Machines Corporation, is one example of such a microprocessor implemented mainframe. This particular desktop system is a hardware/software package that allows one to run System/370 application programs in a single user environment, to run as a terminal attached to a mainframe host or to run in a stand-alone mode as a personal computer, as required by the particular application. There are, of course, similar systems available from other manufacturers, all of which systems incorporate many of the same functions as the Personal Computer XT/370 although the manner and means of implementation does differ, in varying degrees, from system to system.
Due to revolutionary advances in chip densities and packaging, which have been accompanied by significant reductions in costs, many main frame features can now be implemented directly in a desktop system, while other features require some hardware and/or software assistance in order to make them available. The introduction and use of more powerful microprocessors such as, for example, the 8086 and 8088 from Intel Corporation and the 68000 from Motorola Corporation, add further to the list of functions it would be possible to implement in a desktop mainframe. This new breed of microprocessors is fully capable of running a large, enriched instruction set, such as that of System/370, although several of these microprocessors, working in concert with the aid of additional hardware and/or software support, would be required to effect instruction execution in an acceptable time period. It will also be appreciated that presently available microprocessors, while remarkable for the functions they do offer, are not capable of providing all mainframe capability without system compromise.
Thus, as in all data processing system designs, various trade-offs are made in order to optimize the price and performance of these microprocessor implemented desktop mainframes. One particular trade-off problem is posed by the need or desire to utilize certain mainframe functions and features that would be particularly difficult to provide in a microprocessor implemented desktop mainframe. Another type of trade-off problem is posed by the requirement that all architectural constraints of the emulated mainframe be adhered to so that user programs can be run without conflict. One specific implementation problem of concern, due in part to such trade-offs being made, is that of effecting address translation, from a virtual to a real address, without adversely impacting space and power constraints in a microprocessor implemented mainframe data processing system. In the System/370 world, for example, dynamic address translation (DAT) is implemented with performance as a paramount consideration, with space and power constraints being given secondary weight. In a microprocessor implemented system such design priorities are often reversed and sometimes dramatically so.
Dynamic address translation, by way of background explanation, is a capability which enables the user of a data processing system to have access to a greater working memory size than that which is actually available in terms of physically realized memory. The extra memory size is obtained through the use of a fast mass storage device, such as a hard disk. The memory space perceived to be available by the user is referred to as the virtual memory space. If the data processing system is a multi-user facility or if the size of the application program warrants the use of DAT, part of the user's program will reside in real memory and the rest will reside on the hard disk.
For address translation purposes, the real and virtual memory spaces are partitioned into blocks of equal size called pages. All addresses are divided into two parts; a high order portion that identifies the page number and a low order portion that identifies the address of an element within the page. Given a virtual address, translation to the real address is accomplished by means of a "page table". The page number portion of a virtual address is used to locate the memory residence of a desired page by reference to the page table. If the page table reveals that the desired page is presently in real memory, the virtual page number gets translated to the real page number. The element address within the page remains unchanged. If the desired page is not in real memory, a "page fault" is indicated that causes the desired page to be fetched from the hard disk and loaded into real memory. The page table is then updated to reflect the changes made to real memory.
When a new page is to be loaded into real memory, the position it will occupy is decided by an algorithm that determines which old page can first be removed to make room in real memory for the desired page, with the least impact on system performance. This page selection algorithm is based, in part, on a flag called the reference bit, one of which is associated with each page table entry. The previous contents on the page location being loaded are either written to the hard disk, if the page had been changed since it was first loaded, or simply overwritten, if no page changes have been made. This fact is also determined by software and is indicated by a flag called a change bit, one of which is associated with each page table entry. The reference and change bits are kept in real memory, in a System/370 environment, separate from the page table and pages with which they are associated.
In System/370 architecture, the page table is located in real memory. As a result, due to the relatively slow access times of the real memory chips or modules, translations directly accessing it are extremely slow from a performance standpoint. Therefore, a small subset of the page table is kept in a fast piece of hardware called a translation look-aside buffer (TLB). Address translations are referenced to both the TLB and the page table. If the desired page resides in the TLB, then translation is performed via the TLB and access to the page table is terminated. Otherwise, translation is performed through the page table and the contents of the TLB must be updated. When updating the TLB, reference bits provide a means for determining which address is the least recently used. This address is replaced with the new address obtained via the page table translation. To clear the TLB, a "purge" instruction is given. Performance suffers anytime a translation is performed via the page table because of a "miss" in the TLB.
The above techniques were designed for use in mainframe systems where, as noted above, space and power considerations are secondary to performance. In small, microprocessor-based systems, performance is still important, but space and power considerations becomes significant limiting factors. The address translation problem for the system designer now becomes one of balancing the trade-offs among performance, space and power restrictions while still providing efficient DAT in a single user, microprocessor-based environment.
As was previously mentioned, performing DAT using a page table in a real memory, without a TLB, would result in excessive and relatively slow memory accesses and, thus, degrade system performance. While performance enhancement is made possible in such a situation via implementation of a TLB, this alternative and its associated circuitry utilizes a large amount of high speed logic which requires, in turn, a relatively large quantity as noted, of board space and power. In addition, there is a considerable amount of microcode needed to manage and control operation of the TLB which, if provided, further taxes the limited resources of a microprocessor implemented mainframe. Thus, while it would be possible to enhance address translation to benefit that aspect of system performance, the space, power and coding penalties associated with a TLB-aided solution to translation performance improvement are too great to accept.